1. Field of the Invention
The present invention relates to a method and apparatus for scrambling and descrambling a composite video signal, and more particularly to a method and an apparatus for bit-scrambling and again bit-descrambling a digital signal into which the composite video signal is converted thereby.
2. Description of the Prior Art
There have been various systems for scrambling a composite video signal to prohibit illegally watching TV which is supplied by a commercialized system. Among them, there has been used the most generally a line rotation system wherein the scrambled composite video signal is re-scrambled to be descrambled to be the original composite signal. Accordingly, operation principles of a scrambler and a descrambler are basically the same, and thus the operation principle of the descrambler will be described hereinafter only.
The descrambler employed in the above-mentioned conventional line rotation system is shown in FIG. 1. As shown in the drawing, the descrambler comprises an A/D converter 1 adapted to convert a composite video signal Vin inputted therein into 8 bit digital signals; two line memories 2 and 3 adapted to store the digital signals from said converter 1 alternately; a synchronous divider 4 adapted to divide said composite video signal Vin inputted therein into a horizontal synchronizing signal H.sub.sync and a vertical synchronizing signal V.sub.sync ; a clock generator 5 adapted to generate a sampling clock in response to said horizontal synchronizing signal H.sub.sync from said synchronous divider 4 to apply said sampling clock to said A/D converter 1; a D/A converter 6 adapted to receive and convert the digital signals from said line memories 2 and 3 into an analog signal and to receive the sampling clock from said clock generator 5; a data slicer 7 adapted to extract from said composite video signal Vin initial data coded during a vertical blanking interval VBI thereof for each field thereof in order to generate random numbers; a data RAM 8 adapted to store the coded initial data from said date slicer 7; a microprocessor 9 adapted to decode said coded initial data stored in said data RAM 8; a 10 bit random number generator 10 adapted to receive said vertical synchronizing signal V.sub.sync from said synchronous divider 4 and the decoded initial data from said microprocessor 9 and generate 10 bit random numbers; and an address generator 11 adapted to receive output signals from said 10 bit random number generator 10 and apply address signals to the line memories 2 and 3.
The operation of the descrambler with the above-mentioned construction will now be described.
As shown in FIG. 2A, upon receiving a scrambled composite video signal Vin, the A/D converter 1 converts it into 8 bit digital signals and sends the digital signals out to the line memories 2 and 3 alternately. The line memories 2 and 3 which receive the 8 bit digital signals store them alternately in response to address signals from the address generator 11 and send said stored digital signals out to the D/A converter 6. The D/A converter 6 converts the received digital signals into an analog signal and generates a descrambled composite video signal Vout which is the same as the original composite video signal, as shown in FIG. 2B.
It is noted that address values for the line memories 2 and 3 correspond to a point P shown in FIG. 2B.
A signal of waveform shown in FIG. 2A is scrambled about the point P corresponding to the address values. Accordingly, if a 10 bit random number generator in the scrambler (not shown) which is the same as the 10 bit random number generator 10 generates address values corresponding to the point P on each line randomly, an image from such scrambled video signal can not be recognized at all, like a noise image on screen.
On the other hand, the above-mentioned random number generator of the scrambler as a transmitter transmits the scrambled composite video signal carried with initial data coded during the vertical blanking interval thereof for each field thereof. Accordingly, the data slicer 7 receives the scrambled composite video signal Vin and extracts the coded initial data which is in turn stored into the data RAM 8. The microprocessor 9 decodes the coded initial data stored in the data RAM 8 and supplies it to the 10 bit random number generator 10 as a control signal to control it. Therefore, the value of the point P generated in the scrambler as a transmitter is read precisely by the descrambler as a receiver. This is possible because the scrambler as a transmitter and the descrambler as a receiver have the same construction including the 10 bit random number generator 10 so that if initial data values provided for each field are the same in both devices then the values of the point P generated at each horizontal scanning line are the same in both devices. The generated value for the point P is supplied to the address generator 11 which in turn supplies address signals to the line memories 2 and 3 in order to read a data signal stored in the line memories 2 and 3 as shown in FIG. 2A, as a data signal as shown in FIG. 2B. The reason why two line memories 2 and 3 are used is to perform read and write operations on alternate horizontal lines alternately. Also, the A/D converter 1 and the D/A converter 6 are intended for use of 8 bits and samples of 1024 per horizontal line (10 address lines), although not limited thereto.
In the above conventional construction, however, if the address value for the point P is generated by the random number generator, as above-mentioned, a certain point during the video signal interval corresponding to the point P is cut out and the composite video signal is scrambled about the point P in a line rotation manner. At the cut part of the video signal, a high frequency noise component to be noise is generated. This it results in degrading image quality at the cut part. In addition, there is a disadvantage of expensive manufacture cost which is caused the use of expensive two line memories. Furthermore, it can not prohibit the non-subscribers from watching illegally, because the composite video signal is simply scrambled by using two line memories.